1. Field of this Invention
This invention relates to circuits and methods for generating a stimulus signal and evaluating a response signal for testing of logic and memory located on an integrated circuit. More particularly, this invention relates to circuits and methods for generating test pattern signals and evaluating test response signals to verify operation and function of random access memory (RAM) integrated circuits.
2. Description of Related Art
FIG. 1 shows a typical random access memory (RAM) block diagram. The RAM 150 has address input terminals 141, data input terminals 142 and timing and control input terminals 143. The input decode logic 140 consists of address decoders which convert the address input terminals to array selection lines. These array selection lines can select a single memory bit within the RAM memory array 150 of memory cells or bits. The input decode logic also uses the timing and control input terminals 143 to produce electrical signals which facilitate the selection, reading and writing of the required memory bits. This selection of the memory bits is synchronized to timing clocks 143 so as to synchronize the RAM reading or output and the RAM writing or input with an access clock. This access clock synchronization allows capture of data at input terminals at a specified time with respect to the access clock waveform. It also allows presentation the RAM data at an output terminal 160 or memory read results at a specified time with respect to the access clock waveform.
The most common technique used currently in automatic test pattern generators is the D-algorithm, which is based on path sensitization. The main idea of path sensitization is to select a path through the combinatorial logic from the site of a potential fault to a primary output. Next, a path is followed through the logic circuit from the site of the potential fault to a primary output of the combinatorial logic, specifying the values along this logic path that are required to propagate the signal value on the faulty line to a primary output. The process of propagating a signal through a circuit is called forward drive. Similarly, the process of determining the primary inputs necessary to produce all of the signals required during the forward drive is called the backward trace.
The unique problem of testing sequential logic, which has both combinatorial logic and registers or flip-flops, is solved using scan testing. The idea is to scan in a predefined set of ones and zeros into a set of registers These ones and zeros become the applied inputs to a section or island of combinatorial logic. The results of combination of these inputs through the specified combinatorial logic are captured in output registers. These output registers are connected in a serial chain and can be shifted out serially (scanned out) to allow the testing of the ones and zeros with the expected outputs of the combinatorial section of logic under test. In summary, the D-algorithm is used on the combinatorial islands of logic, which the scan in of the input registers and the scan out of the output registers is used to test the sequential logic designs.
The specific example of memory testing, including dynamic random access memory (DRAM) and static random access memory (SRAM) is understood by reviewing the standard march memory test patterns. A march algorithm has several sets of up/down address settings, read/write operations, read/write data values, and different lengths of read/write data values. The objective of march test patterns is to store and read out alternating ones and zeros in the memory array to check for various known types of memory faults. Some of the memory faults that can be tested and located are stuck-at-one or stuck-at-zero faults, address decoder faults, transition from 1 to 0 and from 0 to 1 faults, stuck open faults, coupling faults, neighborhood pattern sensitive faults, and data retention faults. The required memory test patterns can be presented on parallel inputs, can be scanned in from an external tester via shift registers or can be internally generated via on-chip self test logic.
FIG. 1 also shows other blocks, which serve as testing circuitry for the RAM. A built-in self-test (BIST) circuit 110 represents on-chip self-testing circuit. Typically, this self-testing circuitry provides testing of an entire chip, which includes RAM, logic, and even potentially analog circuitry. The outputs of the BIST go to the RAM test pattern generator 120 and to other test pattern generators 170. This BIST output 180 includes command and background data lines. The command lines instruct the TPG 120, which RAM tests to perform. The background data lines tell the TPG 120 what the expected RAM testing output results should be. Using this command and expected result information, the TPG 120 outputs a serial chain of stimulus or input values 124 to be applied to the RAM under test via the RAM data and control input block 140. The RAM outputs go into the RAM output data and control block 160. These RAM outputs are serially shifted through the test data output 164 into the comparator 130 shown in FIG. 1. In addition, the TPG 120 delivers the expected test pattern results to the comparator 130. The comparator compares the expected results to the actual RAM test results 164 and activates a Pass/Fail output 190 to indicate the results of the compare. The RAM 150 can be replaced by any logic function, and the same on-chip self-test methodology applies. This methodology is typical of the self-test techniques presently in use.
The input decode circuit 140 and the output buffer circuit 160 generally will each include a scan register. The scan register is effectively transparent during normal operation, but allows the transfer of test stimulus signals TS from the test pattern generator TPG 120 to the test access port TAP 144 of the input decode circuit. It is well known in the art that the test stimulus signals are transferred by way of a single connection to the test access port 144 and to the input of the scan registers in the input decode circuit. The normal operational signals, Address 141, Data 142, and timing and control 143 are disabled or alternately controlled by testing circuitry.
The test stimulus signals 124 are “scanned” in the scan register until the test stimulus signals 124 are aligned with the signal path for the normal operational signals. The appropriate timing signals are activated and the input decode circuit performs the operation indicated by the test stimulus signal TS 124. A selected memory cell or cells of the RAM array 180 are written to or read from and the resultant output signals are transferred to the Output Buffer 160
The scan register Output Buffer 160 is connected to the Test Data Output port TDO 164. At the completion of the transfer of the test stimulus TS to the test access port TAP 144, the resultant output signals are “scanned” from the scan registers of the Output Buffer 160 through the Test Data Output port TDO 164 to the Q input of the comparator 130.
The test expected results signal 125 is transferred from the Test Pattern Generator 120 to the comparator 130. The comparator 130 compares the resultant output signals from the test data output port 164 with the test expected result signals 125. The pass/fail signal 135 provides an indication of the success of the comparison. If the test is successful, the pass/fail signal 135 indicates a first logic level (1), and if the test is unsuccessful, the pass/fail signal 135 indicates a second logic level (0).
U.S. Pat. No. 5,377,148 (Rajsuman) describes hardware and methods to test variable size RAMs in a constant period of time. This is accomplished by partitioning the memory array into a plurality of individually accessible equivalently sized memory blocks.
U.S. Pat. No. 5,764,657 (Jones) presents a method for generating an optimal serial test pattern for sequence detection. The serial test pattern comprises a first plurality of bits and is generated by a pattern generator.
U.S. Pat. No. 6,061,817 (Jones et al) presents a method and apparatus for generating a serial test pattern for sequence detection. The serial test pattern has a first plurality of bits and is generated by pattern generator.
U.S. Pat. No. 6,094,738 (Yamada et al.) presents a test pattern generation apparatus and method for an SDRAM by adding a wrap address conversion circuit. Yamada et al. also describes a method of testing SDRAMs by converting address data from the pattern generator to the burst address of predetermined modes.
Kim et al., “On Comparing Functional Fault Coverage and Defect Coverage for Memory Testing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 18, No. 11, November 1999, IEEE, describes the evaluation of the effectiveness of the memory testing algorithms based on the defect coverage by comparing the defect coverage of known memory testing algorithms using the same defect statistics.